1. Technical Field
The present invention relates in general to signal processing, and in particular, to a control system utilizing a nonlinear delta-sigma modulator with switching period error compensation.
2. Description of the Related Art
Many electronic systems utilize nonlinear processes to generate output signals. For example, plant systems, such as servo control systems and power conversion systems, often utilize nonlinear processes. Power control systems often utilize a switching power converter to perform alternating current (AC) to direct current (DC) voltage conversion or to perform DC-to-DC voltage conversion. Switching power converters often includes a nonlinear energy transfer process to provide power factor corrected energy to a load. Power control systems that provide AC-to-DC (or AC-to-AC) conversion often provide power factor corrected and regulated output voltages to many devices that utilize a regulated output voltage.
FIG. 1 illustrates a representative prior art power control system 100, which includes a switching power converter 102. Voltage source 101 supplies an alternating current (AC) input voltage Vin(t) to a full bridge rectifier 103. Voltage source 101 can be, for example, a public utility, and the AC voltage Vin(t) is, for example, a 60 Hz/110 V line voltage in the United States of America or a 50 Hz/230 V line voltage in Europe. Full bridge rectifier 103 rectifies the input voltage Vin(t) and supplies a rectified, time-varying, line input voltage Vx(t) to switching power converter 102.
Switching power converter 102 includes a switch 108 that operates in response to a control signal CS to regulate the transfer of energy from the rectified, time-varying input voltage Vx(t), through inductor 110 to capacitor 106. Switching power converter 102 additionally includes a diode 111 that prevents reverse current flow from capacitor 106 into inductor 110.
Energy transferred through inductor 110 is stored by capacitor 106. Capacitor 106 has sufficient capacitance to maintain an approximately constant voltage VC while providing current to load 112. In at least some implementations, switching power converter 102 is a boost-type converter in which voltage VC is greater than the peak of input voltage Vx(t).
In operation, input current iin varies over time, with a peak input current proportionate to the “on-time” of switch 108 and with the energy transferred to capacitor 106 proportionate to the “on-time” squared. Thus, this energy transfer process is one example of a nonlinear process. In some implementations, switch 108 is an n-channel field effect transistor (FET), and control signal CS is a pulse width modulated (PWM) control signal that causes switch 108 to conduct when the pulse width of CS is high. Thus, in such implementations, the “on-time” of switch 108 is determined by the pulse width of control signal CS, and the energy transferred from Vx(t) to capacitor 106 is proportionate to a square of the pulse width of control signal CS.
Power control system 100 also includes a switch state controller 114 that generates control signal CS with a goal of causing switching power converter 102 to transfer a desired amount of energy to capacitor 106, and thus, to load 112. The desired amount of energy depends upon the voltage and current requirements of load 112. To provide power factor correction close to one, switch state controller 114 generally seeks to control input current iin so that input current iin tracks input voltage Vx(t) while holding capacitor voltage VC constant.
In implementations of switching power converter 102 in which switch 108 is implemented with a FET, one known issue is that the inherent capacitance of the FET undesirably resonates with inductor 110 after input current in inductor 110 is demagnetized. A known technique to minimize such resonance and to reduce the attendant switching losses is so-called “valley switching” in which control signal CS is controlled to turn on switch 108 when the drain voltage VD of the FET reaches it minimum value.
Referring now to FIG. 2, there is depicted a timing diagram of a prior art technique for valley switching implemented by switch state controller 114. In the depicted timing diagram, switch state controller 114 waits for a calculated switching period (TT) to complete and then asserts control signal CS to turn on switch 108 after some delay TTerr in order to hit the valley of drain voltage VD. As shown in FIG. 2, this control technique results in an extension of switching period TT by TTerr to a obtain a switching period of TT′.
As can be seen from FIG. 2, the conventional valley switching technique leads to a reduction in the average current supplied to load 112 to less than the intended amount. In particular, the intended output current supplied to the load is given as IoutTT=Q2/TT, while in practice the actual output current is given as IoutTT′=Q2/TT′. That is, because TTerr is always positive in valley switching, IoutTT′ is always less than IoutTT. The drop in output current IoutTT′ ultimately leads to a reduction in the maximum output power that can be delivered to load 112.